사양
| 속성 | 가치 |
| Supplier | Intel |
| Package | Tray |
| Series | MAX® 9000A |
| ProductStatus | Obsolete |
| ProgrammableType | In System Programmable |
| DelayTimetpd(1)Max | 10 ns |
| VoltageSupply-Internal | 4.5V ~ 5.5V |
| NumberofLogicElements/Blocks | 20 |
| NumberofMacrocells | 320 |
| NumberofGates | 6000 |
| NumberofI/O | 60 |
| OperatingTemperature | -40°C ~ 85°C (TA) |
| MountingType | Surface Mount |
| Package/Case | 84-LCC (J-Lead) |
개요
Description
EPM9320ALI84-10 is an Altera CPLD (EPM9320AL family) in an 84-pin package with speed grade -10. It provides a fixed array of programmable macrocells and interconnects to implement glue logic, finite-state machines, decoders, and simple interfaces. It is a non-volatile logic device (configuration memory retained after power-down) and does not include embedded RAM. Features typically include multiple I/O pins with programmable drive and I/O standards (varies by variant), and a straightforward clocking/topology suitable for timing-critical logic. Programming is done with Altera/Intel tools (Quartus II or older MAX+PLUS II) using Verilog/VHDL or schematic entry; configuration via standard programmers or JTAG. Common application areas are interface bridging, control logic, and other small, deterministic digital circuits. For exact electrical specs, I/O standards, power, and timing, consult the official EPM9320AL datasheet and package documentation.
Features
EPM9320ALI84-10 is a Altera MAX 3000A CPLD. Key features (concise):
- Macrocell count: about 320 macrocells
- Package: 84-pin (ALDI84 variant)
- Speed grade: -10 (10 ns)
- I/O: 5V-tolerant digital I/O, up to roughly 60 I/O pins total
- Programmability: in-system via JTAG or Active Serial programming
- Clocking/interconnect: built-in global clock buffers and programmable interconnect for flexible logic routing
- Architecture: programmable logic blocks with combinational and sequential elements (no dedicated external memory on chip)
- Operating voltage: typically 4.5–5.5V
- Typical use: glue logic, simple state machines, small interfacing tasks
Note: exact I/O counts and voltage/temperature ranges vary by specific package/variant. For precise specs, consult the official datasheet for EPM9320ALI84-10.
- Macrocell count: about 320 macrocells
- Package: 84-pin (ALDI84 variant)
- Speed grade: -10 (10 ns)
- I/O: 5V-tolerant digital I/O, up to roughly 60 I/O pins total
- Programmability: in-system via JTAG or Active Serial programming
- Clocking/interconnect: built-in global clock buffers and programmable interconnect for flexible logic routing
- Architecture: programmable logic blocks with combinational and sequential elements (no dedicated external memory on chip)
- Operating voltage: typically 4.5–5.5V
- Typical use: glue logic, simple state machines, small interfacing tasks
Note: exact I/O counts and voltage/temperature ranges vary by specific package/variant. For precise specs, consult the official datasheet for EPM9320ALI84-10.
Pinout
- Pin count: 84 pins (84-pin package)
- Function: Altera EPM9320ALI84-10 is an EPLD/CPLD device (320 macrocells) used to implement configurable digital logic (glue logic, small to mid-size logic circuits).
- Function: Altera EPM9320ALI84-10 is an EPLD/CPLD device (320 macrocells) used to implement configurable digital logic (glue logic, small to mid-size logic circuits).
Manufacturer
- Manufacturer: Altera Corporation (now part of Intel, Intel FPGA).
- What kind of company: A semiconductor company that designs and manufactures programmable logic devices (PLDs), including EPLDs/CPLDs and FPGAs, along with related software and IP.
- What kind of company: A semiconductor company that designs and manufactures programmable logic devices (PLDs), including EPLDs/CPLDs and FPGAs, along with related software and IP.
Application
Typical application areas for the EPM9320ALI84-10 (a CPLD) include:
- Glue logic for microprocessor/microcontroller systems
- Address/data decoding and memory/I/O decoders
- Finite state machines and timing/control sequencing
- Peripheral interfaces and protocol bridges (SPI, I2C, parallel buses)
- Clock distribution and skew/timing management
- Simple display drivers (LEDs, LCDs)
- Data path multiplexing/demultiplexing and interconnect logic
- Prototyping and low-volume custom logic in embedded designs
These cover most small to mid-size digital logic tasks in embedded projects.
- Glue logic for microprocessor/microcontroller systems
- Address/data decoding and memory/I/O decoders
- Finite state machines and timing/control sequencing
- Peripheral interfaces and protocol bridges (SPI, I2C, parallel buses)
- Clock distribution and skew/timing management
- Simple display drivers (LEDs, LCDs)
- Data path multiplexing/demultiplexing and interconnect logic
- Prototyping and low-volume custom logic in embedded designs
These cover most small to mid-size digital logic tasks in embedded projects.
Package
84-pin FineLine LQFP (84-pin thin quad flat package).