사양
| 속성 | 가치 |
| Supplier | AMD Xilinx |
| Package | Tube |
| Series | XC9500 |
| ProductStatus | Obsolete |
| ProgrammableType | In System Programmable (min 10K program/erase cycles) |
| DelayTimetpd(1)Max | 10 ns |
| VoltageSupply-Internal | 4.75V ~ 5.25V |
| NumberofLogicElements/Blocks | 4 |
| NumberofMacrocells | 72 |
| NumberofGates | 1600 |
| NumberofI/O | 34 |
| OperatingTemperature | 0°C ~ 70°C (TA) |
| MountingType | Surface Mount |
| Package/Case | 44-LCC (J-Lead) |
개요
Description
The XC9572-10PC44C is a Xilinx CPLD from the XC9500 family. It’s a small, early programmable logic device intended for glue logic, simple state machines, decoders, and interface control in embedded designs.
Key points
- 72 macrocells (programmable logic resources) with a flexible interconnect.
- Package: PLCC44 (44-pin) in the PC44C family variant.
- Speed grade: -10 (moderate/older-speed part; exact timing depends on design and I/O loads).
- Non-volatile configuration: programmed with Xilinx tools and typically configured at power-up from a programmer or external PROM; supports in-system/ JTAG programming on many configurations.
- Typical use cases: glue logic between microcontrollers and peripherals, small decoders, pulse/handshake controllers, simple finite-state machines.
Notes
- It’s an older device; for new designs, consider modern CPLDs or FPGAs with updated tooling and integration options. Check the datasheet for exact I/O counts, timing, and package pinout before selecting for a design.
Key points
- 72 macrocells (programmable logic resources) with a flexible interconnect.
- Package: PLCC44 (44-pin) in the PC44C family variant.
- Speed grade: -10 (moderate/older-speed part; exact timing depends on design and I/O loads).
- Non-volatile configuration: programmed with Xilinx tools and typically configured at power-up from a programmer or external PROM; supports in-system/ JTAG programming on many configurations.
- Typical use cases: glue logic between microcontrollers and peripherals, small decoders, pulse/handshake controllers, simple finite-state machines.
Notes
- It’s an older device; for new designs, consider modern CPLDs or FPGAs with updated tooling and integration options. Check the datasheet for exact I/O counts, timing, and package pinout before selecting for a design.
Equivalent
There is no exact cross‑reference. XC9572-10PC44C is a 72-macrocell CPLD from Xilinx’s 9500XL family in a PLCC44 package, with no pin‑for‑pin equivalent from other vendors. Closest non‑drop‑in options in PLCC44 by capacity are Lattice ispLSI/ispMACH parts (e.g., ispLSI 2032) and Altera MAX 7000A devices; however, pinout, timing and features differ, so a redesign is usually required. For exact substitutes, use a distributor’s cross-reference tool.
Features
Here are the main features of XC9572-10PC44C (Xilinx 9500 CPLD, PLCC-44):
- 72 macrocells for combinational/ sequential logic
- 44-pin PLCC package (PC44)
- 5V operation; TTL/CMOS input/output levels
- Speed grade -10
- JTAG boundary-scan for programming and testing; in-system reprogrammable
- Configurable via external PROM or serial/ISP download (Master/Slave serial configuration)
- Macrocell structure: each macrocell contains a D-type flip-flop and a programmable function (LUT-based)
- Dozens of I/O pins available in this package (typical usage ~32 I/O, varies by design)
- Suitable for glue logic, small state machines, and simple interfacing tasks in a single CPLD device
Note: exact I/O count depends on I/O usage and package constraints.
- 72 macrocells for combinational/ sequential logic
- 44-pin PLCC package (PC44)
- 5V operation; TTL/CMOS input/output levels
- Speed grade -10
- JTAG boundary-scan for programming and testing; in-system reprogrammable
- Configurable via external PROM or serial/ISP download (Master/Slave serial configuration)
- Macrocell structure: each macrocell contains a D-type flip-flop and a programmable function (LUT-based)
- Dozens of I/O pins available in this package (typical usage ~32 I/O, varies by design)
- Suitable for glue logic, small state machines, and simple interfacing tasks in a single CPLD device
Note: exact I/O count depends on I/O usage and package constraints.
Pinout
- Pin count: 44 pins (44-pin plastic package)
- Function: Xilinx XC9572-10PC44C is a 72‑macrocell CPLD (XC9500XL family) used to implement digital logic/glue logic in a small 44-pin package (speed grade -10).
- Function: Xilinx XC9572-10PC44C is a 72‑macrocell CPLD (XC9500XL family) used to implement digital logic/glue logic in a small 44-pin package (speed grade -10).
Manufacturer
- Manufacturer: Xilinx, Inc. (now part of AMD)
- What kind of company: An American multinational semiconductor company that designs and manufactures programmable logic devices (FPGAs and CPLDs) and related software/IP.
- What kind of company: An American multinational semiconductor company that designs and manufactures programmable logic devices (FPGAs and CPLDs) and related software/IP.
Application
XC9572-10PC44C is a low-cost 72-macrocell CPLD from Xilinx (XC9500 family). Common application areas include:
- Glue logic and small control units on PCBs
- Finite-state machines and sequencing logic
- Address decoding and peripheral interfacing in microprocessor systems
- Simple timing generators, counters, and pulse shaping
- Protocol interfaces and buffering (SPI, I2C, UART) and data-path arbitration
- LED/LCD display control and scanning
- Keyboard scan and debounce logic
- Replacing multiple TTL gates/ASICs in consumer, automotive, and industrial equipment
- Glue logic and small control units on PCBs
- Finite-state machines and sequencing logic
- Address decoding and peripheral interfacing in microprocessor systems
- Simple timing generators, counters, and pulse shaping
- Protocol interfaces and buffering (SPI, I2C, UART) and data-path arbitration
- LED/LCD display control and scanning
- Keyboard scan and debounce logic
- Replacing multiple TTL gates/ASICs in consumer, automotive, and industrial equipment
Package
It’s a 44-pin PLCC package (Plastic Leaded Chip Carrier), i.e., PLCC-44, with commercial temperature range.
